The present invention relates to an information processing system for multitasking.
A first method of accomplishing synchronization between instruction processors, which perform parallel processing (or multitasking), is disclosed in U.S. Pat. No. 4,636,942 entitled "COMPUTER VECTOR MULTIPROCESSING CONTROL" and issued Jan. 13, 1987. In the method disclosed by this patent, a one-bit semaphore register used in common by all of processors is provided and a test and set instruction is provided for the semaphore register. A processor having executed a test and set instruction stops to issue the succeeding instruction during a time when the semaphore register is "0" or until the semaphore register is set to "1" by another processor. Thus, high-speed synchronization is accomplished by synchronizing one of processors with the other processor with allowing the processor to test the semaphore register continually.
As a second method of accomplishing high-speed synchronization between parallel-processing (or multitasking) processors is known by the following technique. Namely, a compare instruction and a branch instruction are combined to form a spin loop and the number of times of looping is set to a predetermined value. When the predetermined number of times of looping is reached, the spin loop is passed through and the control is delivered to an operating system (OS) by a supervisor call. One example will described by use of known instructions employed by the M series processor. In this instruction sequence, the number 100 of times of looping is set to GR2 for a wait for the content of SEMAPHORE to take "1" through the spin loop.
______________________________________ L GR3, = F'1' L GR2, = F'100' LABEL1 C GR3, SEMAPHORE BE LABEL2 BCT GR2, LABEL1 SVC LABEL2 NOP ______________________________________
The above-mentioned prior art involves the following problems.
In the first conventional method in which the synchronization is accomplished between processors, the execution of a test and set instruction is infinitely continued with each processor being exclusively used until the semaphore register is set to "1". Under a multi-job environment, however, there may take place the case where another job can be executed with the intervention of an operating system (OS) in a time until the semaphore register is set to "1". Therefore, especially in the multi-job environment, the first method has a problem that the system throughput is deteriorated.
In the second conventional method, on the other hand, the problem in the first problem does not arise since the number of times of spin looping is set. In a multi-job environment, however, since a job subjected to parallel processing and another job are executed in a co-existing form, a time required for synchronization may differ at every execution. Namely, since a CPU time differs at every execution, an account is not stabilized or the tuning of a program cannot be made. This problem does not arise if it is possible to measure a time required for synchronization so as to determine a CPU time from which the time required for synchronization is subtracted. In the second conventional method, however, the measurement of the time required for synchronization needs executing supervisor call instructions upon start and end of a spin loop to generate supervisor call interruptions and obtaining information of CPU times consumed at both the points of time from an OS to determine a difference therebetween. But, there is a problem that the generation of interruptions results in a very large overhead, thereby losing the significance of the performation of a high-speed synchronization processing by the spin loop with the exclusive possession of each processor being taken.
The second conventional method further has the following problem.
In general, each processor is provided with a buffer storage to contemplate high-speed execution of an instruction. The copy of a part of a main storage is held in the buffer storage. In the case when a multitasking is performed while accomplishing synchronization between a plurality of processors, the synchronization must be accomplished by use of common data such as the above-mentioned SEMAPHORE which exists at the same position in the main storage. Namely, the synchronization is accomplished in such a manner that a first processor waits for SEMAPHORE to become "1" and a second processor stores "1" into SEMAPHORE.
The buffer storage in the first processor holds the copy of the content of SEMAPHORE in the main storage, thereby contemplating a high-speed processing for comparison. Accordingly, when the second processor rewrites the content of SEMAPHORE in the main storage into "1", SEMAPHORE held by the buffer storage in the first processor is invalidated. As a result, when the first processor makes again the comparison of the content of SEMAPHORE with "1", the copy of SEMAPHORE in the main storage is not present in the buffer storage in the first processor. Therefore, the judgement of the accomplishment of synchronization can be made by performing a comparison processing after the content of SEMAPHORE as newly rewritten has been block-transferred from the main storage to the buffer storage.
Thus, since the block transfer occurs when SEMAPHORE becomes "1" and the synchronization is accomplished, the second conventional method involves a problem that a long time is required from the accomplishment of synchronization until the execution of the next instruction. On the other hand, if a method is employed in which the content of SEMAPHORE is fetched directly from the main storage, there is no occurrence or need of block transfer upon accomplishment of synchronization though it is not possible to perform a comparison processing itself at a high speed.